1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display (LCD) device and a method of manufacturing the same.
2. Discussion of the Related Art
Until recently, display devices have typically used cathode-ray tubes (CRTs). Presently, many efforts and studies are being made to develop various types of flat panel displays, such as liquid crystal display (LCD) devices, plasma display panels (PDPs), field emission displays, and electro-luminescence displays (ELDs), as a substitute for CRTs. Of these flat panel displays, LCD devices have many advantages, such as high resolution, light weight, thin profile, compact size, and low voltage power supply requirements.
In general, an LCD device includes two substrates that are spaced apart and face each other with a liquid crystal material interposed between the two substrates. The two substrates include electrodes that face each other such that a voltage applied between the electrodes induces an electric field across the liquid crystal material. Alignment of the liquid crystal molecules in the liquid crystal material changes in accordance with the intensity of the induced electric field into the direction of the induced electric field, thereby changing the light transmissivity of the LCD device. Thus, the LCD device displays images by varying the intensity of the induced electric field.
FIG. 1 is a schematic view illustrating an array substrate of an LCD device according to the related art.
Referring to FIG. 1, the array substrate includes a display region AA to display images and a non-display region NAA. The array substrate 10 includes first to mth gate lines GL1 to GLm and first to nth data lines DL1 to DLn crossing each other on a substrate 10 to define a plurality of pixel regions P in the display region AA. A thin film transistor T is in each pixel region P and connected to the corresponding gate and data lines, and a pixel electrode 80 is in each pixel region P and connected to the thin film transistor T.
In the non-display region NAA, the array substrate includes first to mth gate link lines GLL1 to GLLm and first to nth data link lines DLL1 to DLLn, first to mth gate pads GP1 to GPm connected to the first to mth gate link lines GLL1 to GLLm, respectively, first to nth data pads DP1 to DPn connected to the first to nth data link lines DLL1 to DLLn, respectively. The first to mth gate lines GL1 to GLm are connected to the first to mth gate link lines GLL1 to GLLm, respectively, and the first to nth data lines DL1 to DLn are connected to the first to nth data link lines DLL1 to DLLn, respectively.
The gate pads GP1 to GPm and the data pads DP1 to DPn are attached to gate and data driving portions, for example, through a TAB (tape automated bonding) process. Accordingly, gate and data signals are supplied from the driving portions to the gate and data lines GL1 to GLm to DL1 to DLn.
In the related art, the gate lines, the gate link lines and the gate pads are formed at the same layer, and the data lines, the data link lines and the data pads are formed at the same layer. Accordingly, there is a limit to reducing an area of the non-display region. This problem is explained as follows.
FIG. 2 is a view enlarging a portion A of FIG. 1.
Referring to FIG. 2, in a display region AA, gate lines include odd and even gate lines 20a and 20b alternately arranged on a substrate 10, and data lines include odd and even data lines 30a and 30b alternately arranged.
A thin film transistor T includes a gate electrode 25, a semiconductor layer 40 on the gate electrode 25, and source and drain electrodes 32 and 34 on the semiconductor layer 40. The semiconductor layer 40 includes an active layer made of intrinsic amorphous silicon and an ohmic contact layer made of extrinsic amorphous silicon. A pixel electrode 80 in a pixel region P is connected to the drain electrode 34.
A non-display region NAA includes a data link region DLA, and a data pad region DPA. In the data link region DLA, data link lines include odd and even data link lines 50a and 50b alternately arranged. In the data pad region DPA, data pads include odd and even data pads. The odd data pad include an odd data pad electrode 60a and an odd data pad terminal electrode 70 connected to the odd data pad electrode 60a through an odd data pad contact hole DPH1. The even data pad include an even data pad electrode 60b and an even data pad terminal electrode 70b connected to an even data pad contact hole DPH2.
The odd and even data lines 30a and 30b, the odd and even data link lines 50a and 50b, and the odd and even data pad electrodes 60a and 60b are formed at the same layer.
To reduce an area of the non-display region NAA, it is suggested to reduce areas of the data pads. This, however, causes increase of resistance of the data pad and delay of the data signal, and thus, display degradation, for example, afterimage occurs.
Alternatively, when a width CD of the data link line is reduced, this causes increase of resistance of the data link line and delay of the data signal. Accordingly, reduction of the width of the data link line has a limit.
Alternatively, it has been suggested to reduce an area of the data link region DLA and form the data pad region DPA closer to the display region AA. This involves reducing distances P1, P2 and P3 between the data link lines. As the distances are reduced, the data link lines may be subject to a short-circuit due to conductive particles, which are in a process chamber, stuck to the data link lines.
These problems make it difficult to reduce the area of the non-display region.